A Module of I2C Master for FPGA/CPLD in Verilog HDL

1. Finite-State Machine

2. RTL Structure

3. Experimental System

An experimental system is setup using a DE10-nano development kit and a 4-channel oscilloscope.

a. Waveform of writing operation

The Master module writes 3 bytes of data to an I2C slave module (address 0x70).

b. Waveform of reading operation

The Master module reads 3 bytes of data from an I2C slave module (address 0x70).