{"id":644,"date":"2021-04-04T23:20:47","date_gmt":"2021-04-04T16:20:47","guid":{"rendered":"https:\/\/bigdolphin.com.vn\/?p=644"},"modified":"2024-03-26T15:26:56","modified_gmt":"2024-03-26T08:26:56","slug":"ip-core-for-interfacing-between-wireless-ps2-playstation-and-de10-nano","status":"publish","type":"post","link":"https:\/\/bigdolphin.com.vn\/?p=644","title":{"rendered":"IP Core for interfacing between PS2 Controller and DE10-nano"},"content":{"rendered":"\n

1. Pinout of PS2 Controller<\/strong><\/h3>\n\n\n\n
\"\"<\/figure><\/div>\n\n\n\n

2. Connection to DE10 nano<\/strong><\/h3>\n\n\n\n
    \n
  • DATA -> GPIO_1[4]<\/li>\n
  • ATTENTION (CS) -> GPIO_1[3]<\/li>\n
  • CLOCK -> GPIO_1[1]<\/li>\n
  • COMMAND -> GPIO_1[5]<\/li>\n<\/ul>\n\n\n\n
    \n
    \n
    \"\"<\/figure><\/div>\n<\/div>\n\n\n\n
    \n
    \"\"<\/figure><\/div>\n<\/div>\n<\/div>\n\n\n\n

    3. System Verilog<\/strong><\/h3>\n\n\n\n

    a. IP core<\/strong><\/p>\n\n\n\n

    \"\"<\/figure><\/div>\n\n\n\n

    b. Internal registers<\/strong><\/p>\n\n\n\n

    parameter<\/strong> counterBitMax = 96<\/strong>;\nreg<\/strong>    [counterBitMax:0<\/strong>]       status;\nreg<\/strong>                            signal_clk;\nreg<\/strong>                            signal_cmd;\nreg<\/strong>                            signal_data;\nreg<\/strong>                            signal_att;\nreg<\/strong>    [            6<\/strong>:0<\/strong>]       counterCLK;\nreg<\/strong>    [           17<\/strong>:0<\/strong>]       counterATT;\nreg<\/strong>    [counterBitMax:0<\/strong>]       Data_cmd;\nreg<\/strong>    [            7<\/strong>:0<\/strong>]       counterBit;<\/code><\/pre>\n\n\n\n
    c. Logic control and clock generator<\/strong><\/p>\n\n\n\n
    • Activating Attention every 50ms.<\/li>
    • In each period of 50ms, generate clock to read 96 bit.<\/li>
    • Deactivating Attention after transferring 96 bit data completely.<\/li>
    • The IP core uses 3.072 MHz clock.<\/li><\/ul>\n\n\n\n
      \/\/ Generating SCLK generation and Controlling ATT\nalways_ff @ (posedge clk_3072) begin\n\u00a0\u00a0\u00a0\u00a0if (reset) begin\n \u00a0\u00a0\u00a0 \u00a0\u00a0\u00a0counterATT <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0signal_att <= 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0counterCLK <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0signal_clk <= 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0counterBit <= 0;\n\u00a0\u00a0\u00a0\u00a0end\n\u00a0\u00a0\u00a0\u00a0else begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0if (counterATT > 153600) begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    counterATT <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    signal_att <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    counterCLK <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    signal_clk <= 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    counterBit <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0end\n  \u00a0\u00a0\u00a0 \u00a0\u00a0else begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    if (counterBit > counterBitMax) begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        signal_att <= 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        counterCLK <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        signal_clk <= 1'b1; \u00a0\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    end\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    else begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        signal_att <= 0; \u00a0\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        if (counterCLK > 77) begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0            counterCLK <= 0;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0            signal_clk <= ~signal_clk;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0            if (signal_clk) begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0                counterBit <= counterBit + 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0            end\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        end\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        else begin\n  \u00a0\u00a0\u00a0 \u00a0\u00a0            counterCLK <= counterCLK + 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0        end \u00a0\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    end \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\n  \u00a0\u00a0\u00a0 \u00a0\u00a0    counterATT <= counterATT + 1'b1;\n  \u00a0\u00a0\u00a0 \u00a0\u00a0end \u00a0\u00a0\n\u00a0\u00a0\u00a0\u00a0end\nend<\/code><\/pre>\n\n\n\n
      d. Write to controller<\/strong><\/p>\n\n\n\n
      \/\/ Write to Controller\nalways_ff<\/strong>\u00a0@ (negedge<\/strong>\u00a0signal_clk) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0if<\/strong>\u00a0(reset) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0signal_cmd <=\u00a0'x<\/strong>;\n\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0else<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0signal_cmd <=\u00a0Data_cmd[counterBit];\nend<\/strong><\/code><\/pre>\n\n\n\n
      e. Read from controller<\/strong><\/p>\n\n\n\n
      \/\/ Read from Controller\nalways_ff<\/strong>\u00a0@ (negedge<\/strong>\u00a0signal_clk) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0if<\/strong>\u00a0(reset) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0status <=\u00a00<\/strong>;\n\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0else<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0status[counterBit] <=\u00a0signal_data;\nend<\/strong><\/code><\/pre>\n\n\n\n
      f. Send data to Avalon<\/strong><\/p>\n\n\n\n
      \/\/ Read operations performed on the Avalon-MM Slave interface\nalways_ff<\/strong>\u00a0@ (posedge<\/strong>\u00a0clk) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0if<\/strong>\u00a0(reset) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0avs_s0_readdata <=\u00a0'x<\/strong>;  \u00a0\n\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0else<\/strong>\u00a0if<\/strong>\u00a0(avs_s0_read) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0case<\/strong>\u00a0(avs_s0_address)\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd0<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0avs_s0_readdata <=\u00a0status[31<\/strong>:0<\/strong>];\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd1<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0avs_s0_readdata <=\u00a0status[63<\/strong>:32<\/strong>];\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd2<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0avs_s0_readdata <=\u00a0status[95<\/strong>:64<\/strong>];\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default<\/strong>\u00a0:\u00a0avs_s0_readdata <=\u00a0'x<\/strong>;\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0endcase<\/strong> \n\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0else<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0avs_s0_readdata <=\u00a0'x<\/strong>;\nend<\/strong><\/code><\/pre>\n\n\n\n
      g. Build command from data which is sent from Avalon<\/strong><\/p>\n\n\n\n
      \/\/ Write operations performed on the Avalon-MM Slave interface\nalways_ff<\/strong>\u00a0@ (posedge<\/strong>\u00a0clk) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0if<\/strong>\u00a0(reset) begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Data_cmd <=\u00a0{{80<\/strong>{1'b0<\/strong>}},8'h42<\/strong>,8'h01<\/strong>};\n\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0else<\/strong>\u00a0begin<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if<\/strong>\u00a0(avs_s0_write) begin<\/strong>  \u00a0\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0case<\/strong>\u00a0(avs_s0_address)\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd0<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0Data_cmd[31<\/strong>:0<\/strong>] <=\u00a0avs_s0_writedata;\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd1<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0Data_cmd[63<\/strong>:32<\/strong>] <=\u00a0avs_s0_writedata;\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a02'd2<\/strong>\u00a0\u00a0\u00a0\u00a0:\u00a0Data_cmd[95<\/strong>:64<\/strong>] <=\u00a0avs_s0_writedata;\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0default<\/strong>\u00a0:\u00a0Data_cmd <=\u00a0{{80<\/strong>{1'b0<\/strong>}},8'h42<\/strong>,8'h01<\/strong>};\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0endcase<\/strong>\n\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0end<\/strong>\n\u00a0\u00a0\u00a0\u00a0end<\/strong>\nend<\/strong><\/code><\/pre>\n\n\n\n
      h. Assign logic states<\/strong><\/p>\n\n\n\n
      assign<\/strong>\u00a0ps_cs \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0=\u00a0signal_att;\nassign<\/strong>\u00a0ps_clk \u00a0\u00a0\u00a0\u00a0\u00a0=\u00a0signal_clk;\nassign<\/strong>\u00a0ps_cmd \u00a0\u00a0\u00a0\u00a0\u00a0=\u00a0signal_cmd;\nassign<\/strong>\u00a0signal_data =\u00a0ps_dat;<\/code><\/pre>\n\n\n\n
      4. C\/C++ code to communicate with the IP core<\/h3>\n\n\n\n
      \/* Playstation wireless *\/\nprintf(\"\\r\\n<\/strong>---> Playstation IP...\\r\\n<\/strong>\");\nplaystation_ip_map =\u00a0getBASE(virtual_base,ALT_LWFPGASLVS_OFST,PLAYSTATION_WIRELESS_0_BASE,HW_REGS_MASK);\ni =\u00a00<\/strong>;\nwhile<\/strong>(1<\/strong>){ \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\n\u00a0\u00a0\u00a0\u00a0printf(\"[%d] playstation_ip_map @ LW = 0x%08X,%08X,%08X @ %X\\r\\n<\/strong>\",i,*(playstation_ip_map +\u00a00x02<\/strong>),*(playstation_ip_map +\u00a00x01<\/strong>),*playstation_ip_map,(uint32_t<\/strong>)playstation_ip_map);\n\u00a0\u00a0\u00a0\u00a0i++;\n\u00a0\u00a0\u00a0\u00a0\/\/ Wait 0.2s\n\u00a0\u00a0\u00a0\u00a0usleep(200000<\/strong>);\n}<\/code><\/pre>\n\n\n\n
      5. Testing<\/h3>\n\n\n\n
      \n